Optimal processor assignment for pipeline computations

The availability of large scale multitasked parallel architectures introduces the following processor assignment problem for pipelined computations. Given a set of tasks and their precedence constraints, along with their experimentally determined individual responses times for different processor sizes, find an assignment of processor to tasks. Two objectives are of interest: minimal response given a throughput requirement, and maximal throughput given a response time requirement. These assignment problems differ considerably from the classical mapping problem in which several tasks share a processor; instead, it is assumed that a large number of processors are to be assigned to a relatively small number of tasks. Efficient assignment algorithms were developed for different classes of task structures. For a p processor system and a series parallel precedence graph with n constituent tasks, an O(np2) algorithm is provided that finds the optimal assignment for the response time optimization problem; it was found that the assignment optimizing the constrained throughput in O(np2log p) time. Special cases of linear, independent, and tree graphs are also considered

Parallel Real-Time Systems* Abstract

For many real-time applications (e.g. Command, Control, and Communications), parallel computers of-fer a natural computing platform. However, very lit-tle attention has been paid to the specification require-ments of real-time systems implemented on parallel ma-chines. Towards this end, we propose a specijlcation language PRETSEL (Parallel REal-Time SpEcification Language). The PRETSEL specification language is based on a traditional two-level view of parallel comput-ing whereby a parallel computation is viewed as a col-lection of interacting (data) parallel algorithms. This view is naturally reflected in PRETSEL syntax where at the lower level various constructs are provided for the specification of a data-parallel real-time algorithm (data-parallelism). At the upper level another set of constructs is provided to combine such tasks in a variety of way (task-parallelism). Furthermore, the PRETSEL language allows for the specification of performance re-quirements. PRETSEL is currently being evaluated for real-time avionics applicaitons. In this paper we de-scribe the sysntax and operational semantics of PRET-SEL and establish results relating the functional and the temporal behaviors.

Energy-aware Allocation of Dynamic Variables in Partitioned Memory Architectures

This paper addresses the problem of minimizing the energy consumption by the memory subsystem in an embedded system. While significant work in the literature has addressed compiler driven energy aware allocation of global static variables, no general solutions have been proposed for the corresponding problem of allocating run-time dynamic variables. This paper proposes an approach, and the corresponding framework, to compiler driven energy aware allocation of dynamic variables. The approach is driven by the use of execution profile information and the concept of heap segmentation. Our framework and solution have been integrated into a compiler backend tool. Experimental results with some benchmark applications indicate that our techniques result in up to 40 % memory energy reduction and 20-25 % overall system energy reduction.

Parallel Real-Time Systems: Formal Specification

For many real-time applications, parallel computers offer a natural computing platform. However, very little attention has been paid to software support for realtime embedded systems on parallel machines. This paper addresses the problem of formal software specification for parallel real-time systems, and presents some features of a formal specification language -- PRETSEL (Parallel REal-Time SpEcification Language). The syntax of PRETSEL is presented and the formal semantic rules are defined. The effectiveness of PRETSEL is demonstrated through the specification of the functionality and timing requirements of a Sonar system. 1 Introduction A number of researchers have observed that complex software systems and especially real-time systems can be made truly robust and reliable if powerful specification and analysis techniques are made available to software developers and maintainers. Subsequently a number of formal models for real-time computing have been proposed and studied. These ..

Fine Grained Register Allocation for EPIC Processors with Predication

In this paper, we study the impact of liveness granularity, the priority function and accurate interference graph construction on register allocation performance on EPIC processors with predication. Fine grained live ranges reduce the number of interferences and hence allow both faster compilation and runtime execution. Similarly, a predicate-aware priority function gives a better register allocation. However, due to the heuristics used in hyperblock formation, predicate aware liveness computations does not result in significant improvements. Keywords: EPIC, ILP, Predicated execution, Region-based Compilation, Register Allocation 1 Introduction Over the past decade, architectural innovations supporting instruction-level parallel processing (ILP) and compiler optimizations that work synergistically with them have become a technological reality[11]. Popularly referred to as explicitly parallel instruction computing or EPIC, key aspects of this technology have influenced the IA-64 arch..